1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to methods and apparatus for testing ion implantation tools for defect mechanisms.
2. Description of the Related Art
The advent of ion implantation marked a major milestone in semiconductor fabrication. Unlike diffusion processes that entail limited control over impurity region geometry and significant consumption of thermal budget, ion implantation promised and delivered the capability of precise geometric positioning of impurity regions with much shallower junctions and without excessive consumption of thermal budget through lengthy anneals. For these reasons, ion implantation has supplanted diffusion in many aspects of impurity region formation in semiconductor processing.
Ion implantation, as the name implies, involves the bombardment of a wafer or substrate surface with a beam of energetic charged atoms or molecules. In currently available ion implanters, the ion beam is formed from a feed source, either a gas or a solid, and accelerated through an acceleration tube. Before striking the target, the ion beam passes through various focusing and scanning apertures. In order to reduce the possibility of charge build up in the implanted surface, a neutralizing beam of electrons is directed into the outgoing ion beam prior to impact with the target surface. The neutralizing beam deionizes a significant quantity of the ions in the ion beam.
Various types of ion implantation processes may be performed at different stages in a given process flow for a semiconductor device. In many cases, the semiconductor wafer undergoes a cleansing bath in which the wafer is subjected to high frequency acoustic pulses. These so-called megasonic baths are designed to liberate contaminants and other unwanted debris left over from the ion implantation and perhaps earlier process steps. A variety of defects have been observed in the circuit structures of semiconductor wafers following megasonic bath cleansing. One type of defect that has been observed some frequency is a missing section or sections of a polysilicon line. Microscopic inspection of such defect sites has revealed that the missing sections are literally torn away from the remaining portions of the polysilicon line. The frequency of such defects has increased as the minimum device geometry or critical dimension of such circuit structures has decreased with improvements in lithography. This at least suggests structural damage due to kinetic collisions as a possible cause for the missing polyline defects.
Latent interactions occurring inside ion implantation tools are suspected as one possible source of the missing polysilicon line defects observed following megasonic bath cleansing. Moving this belief beyond technical suspicion has proved to be difficult. The primary reason is that troubleshooting an ion implantation tool is not a straightforward process. While in operation, ion implantation tools involve a complex interplay of a number of different electric and magnetic fields as well as high velocity spinning parts and particle collisions. The interplay between the various electromagnetic fields, rotating parts and particles within, and the beam geometry, current and energy settings of conventional ion implanters is not well understood.
Conventional methods for investigating the impact of ion implanter settings on wafer defects involve testing the relationship between tool settings and conditions between defects observed on actual product wafers or on bare silicon wafers. In the former case, actual product wafers are pulled from production and used for the diagnostic. This procedure, of course, requires the scrapping of otherwise useable wafers and therefore involves significant loss of potential revenue. The second technique involving the use of bare silicon as a test structure, while less costly than the aforementioned technique, nevertheless may not exhibit sufficient sensitivity to determine causation of suspected ion implantation induced structural defects. If the suspected ion implantation induced structural defects are dependent upon the topography of the implanted structures, then bare silicon test wafers will not adequately reproduce the conditions faced by actual product wafers.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
In accordance with one aspect of the present invention, a method of testing an ion implanter is provided that includes forming a mask with a preselected pattern on a substrate and performing a first scan of the mask to identify any defects thereon. An ion implant is performed on the mask with the ion implanter. Following the ion implant, a second scan of the mask is performed to identify any defects thereon. The first and second scans are compared to identify any defects appearing on the mask following the ion implant.
In accordance with another aspect of the present invention, a method of testing an ion implanter is provided that includes forming a mask with a preselected pattern on a substrate such that the preselected pattern mimics a pattern of circuit structures to be formed in an integrated circuit. A first scan of the mask is performed to identify any defects thereon. An ion implant is performed on the mask with the ion implanter with the ion implanter being set to implant at conditions corresponding to implant conditions to be used in implanting a region of the integrated circuit including the circuit structures. Following the ion implant, a second scan of the mask is performed to identify any defects thereon and the first and second scans are compared to identify any defects appearing on the mask following the ion implant.
In accordance with another aspect of the present invention, an apparatus is provided that includes a substrate and a mask positioned on the substrate that has a pattern of upwardly projecting members. The members have a base and an upper surface. The base is smaller in cross-section than the upper surface whereby the members are mechanically weaker at their bases than at their upper surfaces.
In accordance with another aspect of the present invention, an apparatus is provided that includes a substrate and a mask of insulating material positioned on the substrate. The mask has a preselected pattern mimicking a pattern of circuit structures to be formed in an integrated circuit.